Modern-day electronics systems require multiple patterned layers of electrically or optically active materials, sometimes over a relatively large substrate. Electronics such as radio frequency identification (RFID) tags, photovoltaics, and optical and chemical sensors all require some level of patterning in their electronic circuitry. Flat panel displays, such as liquid crystal displays or electroluminescent displays rely upon accurately patterned sequential layers to form thin film components of the backplane. These electronic components include capacitors, transistors, and power buses. The usual combination of photolithographic patterning methods and selective etch processes has several shortcomings including high cost, difficulty with large substrates, and complexity of selective etch processes.
The feature size obtainable using traditional processing methods is limited by the resolution of the photolithography tools. Currently the minimum feature size for large area display backplanes is around a micron, and requires expensive high end equipment. Minimum feature sizes for large area substrates with less expensive equipment can be much larger. High speed circuit operation requires thin film transistors (TFTs) with high drive current, and many applications additionally require that the drive current be obtained with low voltage operation. It is well known that TFT performance is improved by reducing the channel length. To move beyond the exposure limitation of feature size, vertical transistors of various architectures are currently being studied. In a vertical TFT (VTFT) architecture, the channel is formed perpendicular to the substrate, and therefore the channel length (L) can be controlled by the height of a layer in the transistor.
Recent work in the fabrication of VTFTs, while yielding short channel length devices, has used otherwise standard photolithographic techniques with complex semiconductor processes. For example, since it is not currently possible to put patterns directly on walls which are vertical with respect to the substrate surface, vertical wall patterning has been accomplished using a suitable temporary filler material to partially fill in a trench. The temporary filler material acts as a mask for the portions of the wall located underneath while allowing for processing of the walls above the temporary filler material. This has been used, for example, when an oxide is to be deposited exclusively on vertical walls below a temporary filler material, where the oxide is first deposited or produced over the entire surface of the relief. The relief or trench is initially completely filled with a suitable temporary filler material. Then, the temporary filler material is recessed back to a depth that just covers the desired oxide. After uncovered sections of the oxide are removed, the remaining temporary filler material is removed.
Alternatively, when it is necessary that an oxide be deposited or produced only in upper regions of a vertical wall, an etching stop layer, for example a nitride layer, is first provided over the entire surface of the entire relief pattern. A different material, susceptible to directional etching, for example polycrystalline silicon, is used to fill the relief, and is etched back as far as the desired coverage depth of the final vertical oxide. After the etching stop layer is removed from the unfilled sections of the walls, an oxide is deposited or generated using a thermal technique in the uncovered regions. Next, the oxide is anisotropically etched which removes the deposited oxide from horizontal. This is followed by removal of the filler material and then the removal of the etching stop layer.
In light of the complicated existing processes there is an ongoing need to provide semiconductor device architectures that include patterned vertical or inclined device surfaces. There is also an ongoing need to provide simple manufacturing techniques capable of processing small device features of semiconductor devices without requiring high resolution alignments and small gap printing for vertical TFTs. There is also an ongoing need to provide higher current semiconductor devices by improving the series resistance of the device. To maintain good device performance when shrinking the size of the channel, it is typical to scale the layer thicknesses with the size of the device. For example, conventional production CMOS processes with channel lengths of 90 nm and lower often utilize dielectric layer thicknesses of less than 10 nm. While there are many processes to deposit dielectric materials, few result in high quality films at these thicknesses. Atomic layer deposition (ALD) is a process that is both conformal and known to result in high quality thin layers when used with optimized process conditions.
There is growing interest in combining ALD with a technology known as selective area deposition (SAD). As the name implies, selective area deposition involves treating portion(s) of a substrate such that a material is deposited only in those areas that are desired, or selected. Sinha et al. (J. Vac. Sci. Technol. B 24 6 2523-2532 (2006)), have remarked that selective area ALD requires that designated areas of a surface be masked or “protected” to prevent ALD reactions in those selected areas, thus ensuring that the ALD film nucleates and grows only on the desired unmasked regions. It is also possible to have SAD processes where the selected areas of the surface area are “activated” or surface modified in such a way that the film is deposited only on the activated areas. There are many potential advantages to selective area deposition techniques, such as eliminating an etch process for film patterning, reduction in the number of cleaning steps required, and patterning of materials which are difficult to etch.
SAD work to date has focused on the problem of patterning a single material during deposition. There persists a problem of combining multiple SAD steps to form working devices. Processes for building complete devices need to be able to control the properties of the critical interfaces, particularly in field effect devices like TFTs. There remains a need for novel processes to simplify the manufacture of vertical TFTs, as well as a need for novel processes that use SAD and digital patterning processes to pattern devices which have critical vertical features, such as VTFTs.
A particularly useful electronic device in building functional circuitry is an inverter, which functions to invert the polarity of an input signal. In CMOS circuitry, inverters are typically easy to design but disadvantageously expensive to produce and utilize complicated production processes. It is possible to build all NMOS or PMOS inverters. However, particularly for enhancement-depletion mode circuits there are challenges to independently controlling the behavior of each transistor in the inverter circuit. Typically, the depletion mode transistor will have a thicker semiconductor layer than the enhancement mode transistor, increasing process complexity and increasing cost. Other alternatives include using dual gate architectures or multilayer semiconductor stacks, which have similar issues of process complexity and cost. As the industry endeavors to build circuitry using printing methods, individual transistor size has a direct impact on the overall circuit footprint, as the individual component transistors are sized using their channel dimensions. There remains a need to build high quality inverters using simple processes, by employing novel architectures to control individual transistor, and therefore, circuit performance.
More generally, there is a need in the industry to have a flexible process that enables facile fabrication of the components of any electronic circuit. Processes required to form short channel devices have previously been incompatible with processes used to form longer channel devices. There is a need to be able to mix and match components for the best circuit design—rather than being limited by the capabilities of conventional processes.